High-speed analogue multipliers are often used as parts of high-speed linear equalisers (LE) and/or decision feedback equalisers (DFE) to compensate distortions caused by of optical fibres in optical transmission lines. These multipliers function as variable gain amplifier and must be linear over a wide frequency range. The high-speed requirements of optical transmission lines need high-speed electronic components, which circuits must be designed for advanced semiconductor technologies at their speed edges. But it is essential for the function of an LE or DFE, that the high frequency parts of an RF-signal as well as the low frequency parts were multiplied with the same coefficient or weight. On the other hand, the bandwidth of analogue multipliers used for weighting (damping or amplifying) an RF-signal decreases at lower coefficients rapidly or increases at higher coefficients with gain peaks at high frequencies.
The reasons for this behaviour are the parasitic capacitances at the output nodes of the multiplier (see Cpar in FIG. 1) and the decreasing currents to charge and discharge these at lower coefficient input voltages. Caused by decreasing coefficient input voltage the output voltage decreases because the resultant currents in the load resistors R1 and R2 are decreasing, too (iR1=iQ0−iQ2). This effect is mitigated by the decreasing amplitude of the output voltage but the bandwidth loss is greater.
A well known possibility to increase the bandwidth of analogue multipliers is the use of so called peaking capacitors shown as capacitor C1 in FIG. 1.
Another solution to achieve a higher bandwidth is the compensation of parasitic capacitances with a compensation circuit as known from EP 1450480 A1 entitled “Low-noise, high-linearity analogue multiplier”.
However, the values of fixed peaking capacitors or a fixed compensation of parasitic capacitances are independent of the variable coefficients used for weighting the analogue RF-signal. If this fixed solution is used to achieve an acceptable bandwidth for low coefficients, the frequency response at high coefficients has an unacceptable gain peak at high frequencies, which leads to additional phase shifts or, at worst cases, to oscillations. If the gain peak at high coefficients is avoided, the bandwidth at low coefficients decreases rapidly and a high linearity at high frequencies cannot be reached.
It is therefore an object of the present invention to provide an analogue multiplier circuit does not show a decrease of bandwidth at low coefficients and which achieves a higher linearity of the RF-signal at high frequencies.